1. Field of the Invention
The present invention relates to zero insertion force sockets which receive and operatively connect one or more semiconductor devices to a carrier substrate. Particularly, the present invention relates to zero insertion force sockets which receive bare or minimally packaged, vertically mountable semiconductor devices. The present invention also relates to semiconductor devices which are mountable substantially perpendicular relative to a carrier substrate and to devices which secure bare or minimally packaged semiconductor devices to a carrier substrate.
2. Background of Related Art
Zero insertion force sockets which operatively attach packaged semiconductor devices to a carrier substrate are known in the art. Typical zero insertion force sockets include resilient contacts which bias against the leads of a package inserted therein. An electrical contact is established between each of the leads and its corresponding contact as the spring force of the contact biases the same against the lead. Exemplary zero insertion force sockets which include resilient contacts are disclosed in the following U.S. Pat. No. 5,466,169, issued to Kuang-Chih Lai on Nov. 14, 1995; U.S. Pat. No. 5,358,421, issued to Kurt H. Petersen on Oct. 25, 1994; U.S. Pat. No. 4,889,499, issued to Jerzy Sochor on Dec. 26, 1989; U.S. Pat. No. 4,710,134, issued to Iosif Korunsky on Dec. 1, 1987; U.S. Pat. No. 4,527,850, issued to Clyde T. Carter on Jul. 9, 1985; U.S. Pat. No. 4,381,130, issued to George J. Sprenkle on Apr. 26, 1983; and U.S. Pat. No. 4,266,840, issued to Jack Seidler on May 12, 1981.
Such devices would not be useful for securing and operatively attaching bare or minimally packaged semiconductor devices to a carrier substrate since the resilient contacts of some such devices are adapted to establish electrical contact with the elongated leads of a packaged semiconductor device, rather than with the bond pads of bare and many minimally packaged semiconductor devices. Other zero insertion force sockets in the prior art include resilient contacts which abut the semiconductor device during insertion of the same into the socket. Thus, the friction generated by the contacts of such zero insertion force sockets would likely scratch or otherwise damage bare semiconductor devices and many minimally packaged semiconductor devices during insertion therein.
Moreover, zero insertion force sockets which include resilient contacts are somewhat undesirable from the standpoint that the contacts tend to lose their resiliency over time and with frequent removal and reinsertion of devices. Thus, the ability of many such zero insertion force socket resilient contacts to establish adequate electrical connections with their corresponding leads of the inserted packaged semiconductor device diminishes over time. Moreover, such resilient contacts may also be damaged while inserting a packaged semiconductor device into the socket.
Other zero insertion force sockets have been developed in order to overcome the above-identified shortcomings of resilient contacts. Many such zero insertion force sockets include contacts which are biased against the leads of a packaged semiconductor device inserted therein by a laterally sliding mechanical actuation device. Examples of such devices are disclosed in the following U.S. Pat. No.: Reissue 28,171, issued to John W. Anhalt; U.S. Pat. No. 4,501,461 on Sep. 24, 1974, issued to John W. Anhalt on Feb. 26, 1985; U.S. Pat. No. 4,397,512 issued to Michele Barraire et al. on Aug. 9, 1983; U.S. Pat. No. 4,391,408, issued to Richard J. Hanlon and Rudi O. H. Vetter on Jul. 5, 1983; and U.S. Pat. No. 4,314,736, issued to Eugene F. Demnianiuk on Feb. 9, 1982.
However, the contacts of many such devices are adapted to establish an electrical connection with the leads of a packaged semiconductor device rather than with the bond pads of a bare or minimally packaged semiconductor device.
Vertical surface mount packages are also known in the art. When compared with traditional, horizontally mountable semiconductor packages and horizontally oriented multi-chip packages, many vertical surface mount packages have a superior ability to transfer heat. Vertical surface mount packages also consume less area on a carrier substrate than a horizontally mounted package of the same size. Thus, many skilled individuals in the semiconductor industry are finding vertical surface mount packages more desirable than their traditional, horizontally mountable counterparts.
Exemplary vertical surface mount packages are disclosed in the following U.S. Pat. No.: Re. 34,794 (the xe2x80x9c""794 patentxe2x80x9d), issued to Warren M. Farnworth on Nov. 22, 1994; U.S. Pat. No. 5,444,304 (the xe2x80x9c""304 patentxe2x80x9d), issued to Kouija Hara and Jun Tanabe on Aug. 22, 1995; U.S. Pat. No. 5,450,289, issued to Yooung D. Kweon and Min C. An on Sep. 12, 1995; U.S. Pat. No. 5,451,815, issued to Norio Taniguchi et al. on Sep. 19, 1995; U.S. Pat. No. 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and U.S. Pat. No. 5,635,760, issued to Toru Ishikawa on Jun. 3, 1997.
The ""794 patent discloses a vertical surface mount package having a gull-wing, zig-zag, in-line lead configuration and a mechanism for mounting the package to a printed circuit board (PCB) or other carrier substrate. The force with which the package mounts to the carrier substrate establishes a tight interference contact between the package""s leads and their corresponding terminals on the carrier substrate.
The ""304 patent describes a vertical surface mount package which has integrally formed fins radiating therefrom. The fins of that device facilitate the dissipation of heat away from the device. The semiconductor device is electrically connected to the package""s leads by wire bonding. The leads of that vertical surface mount package, which extend therefrom in an in-line configuration, are mountable to the terminals of a carrier substrate by soldering.
However, many of the vertical surface mount packages in the prior art are somewhat undesirable from the standpoint that they permanently attach to a carrier substrate. Thus, those vertical surface mount packages are not readily user-upgradable. Moreover, many prior art vertical surface mount packages include relatively long leads, which tend to increase the impedance of the leads and reduce the overall speed of systems of which they are a part. Similarly, the wire bonding typically used in many vertical surface mount packages increases the impedance and reduces the overall speed of such devices. As the speed of operation of semiconductor devices increases, more heat is generated by the semiconductor device, requiring greater heat transfer. Similarly, as the speed of operation of semiconductor devices increases, decreasing the length of the leads regarding circuitry connecting the semiconductor device to other components and, thereby, decreasing the impedance of the leads to increase the responsiveness of the semiconductor device is important.
Thus, a need exists for a zero insertion force alignment device for bare or minimally packaged semiconductor devices which has low impedance and which facilitates the ready removal and reinstallation of the semiconductor devices relative to a carrier substrate. An alignment and attachment device which transfers heat away from the vertical surface mount package and establishes and maintains adequate electrical connections between a vertical surface mount package and a carrier substrate is also needed.
The zero insertion force socket of the present invention addresses each of the foregoing needs. The zero insertion force socket includes intermediate conductive elements which are configured to establish an interference-type electrical connection with the bond pads of a bare or minimally packaged semiconductor device. An actuator moves a plate in the socket to bias the intermediate conductive elements against the bond pads of a semiconductor device without rubbing against the semiconductor device during insertion of the same into the socket.
In a first embodiment of the zero insertion force socket, the actuator moves the plate transversely relative to the socket body to move the intermediate conductive elements into and out of contact with the bond pads of a semiconductor device that is interconnected with the socket.
In a second embodiment of the zero insertion force socket, the actuator moves the plate vertically relative to the socket body in order to actuate movement of the intermediate conductive elements toward and away from the bond pads.
A semiconductor device which is useful in connection with the zero insertion force socket of the present invention includes all of its bond pads along a single edge thereof.
The present invention also includes a method of securing a semiconductor device substantially perpendicularly relative to a carrier substrate, and methods of designing and manufacturing vertically mountable bare semiconductor devices that are useful with the zero insertion force socket of the present invention. A computer with which the zero insertion force socket and the socket-semiconductor device assembly are associated is also within the scope of the present invention.
Advantages of the present invention will become apparent to those of ordinary skill in the relevant art through a consideration of the appended drawings and the ensuing description.